Method and apparatus for coordinating memory operations among diversely-located memory components
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United States of America Patent
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Jan 6, 2004
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Apr 24, 2001
filing date -
Apr 24, 2001
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Abstract
A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
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