Method of manufacturing semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6677230
APP PUB NO 20020182847A1
SERIAL NO

10197411

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Abstract

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A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom ('through holes or local interconnection holes') of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.

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Patent Owner(s)

  • RENESAS ELECTRONICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kawano, Masakazu Tokyo, JP 21 214
Yokoyama, Natsuki Tokyo, JP 74 1440

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