Synchronous communication bus and process for synchronous communication between circuit modules
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United States of America Patent
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Jan 13, 2004
Grant Date -
N/A
app pub date -
Jun 23, 2000
filing date -
Jun 26, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronous communication bus for transferring data between circuit modules (2), which are connected to the communication bus, having at least one data bus (1, 3), a control bus (4) and a bus control unit (5), whereby the circuit modules send an interrupt signal to the bus control unit (5) in order to request data or, respectively, to signal readiness to send data. A memory (6) for the intermediate storage of data is provided in each circuit module (2), whereby the memories (6) are connected to the data bus (1, 3) and the bus control unit (5) is provided for clearing defined memories (6) in order to direct data from selected memories (6) into the data bus (1, 3) or, respectively, from the data bus (1, 3) into the memories (6).
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