Method and device for frequency synthesis using a phase locked loop
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United States of America Patent
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-
Jan 20, 2004
Grant Date -
Oct 17, 2002
app pub date -
May 22, 2002
filing date -
Jun 30, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).
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