Clock synchronous semiconductor memory device
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United States of America Patent
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Jan 20, 2004
Grant Date -
Apr 10, 2003
app pub date -
Jun 18, 2002
filing date -
Oct 5, 2001
priority date (Note) -
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Abstract
The position information indicating the position of a memory relative to a controller is stored in a position information generating circuit, and the transfer timing of write data transmitted from an input circuit to a write circuit and the activation timing of a latch transfer instructing signal are adjusted according to this position information. Thus, the semiconductor memory device is provided that is capable of taking in and generating the internal write data reliably even when the flight time of a data bus becomes substantially the same as the cycle time of a clock signal.
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