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Abstract

A semiconductor memory device that includes an array of memory cells, the memory device operating synchronously with respect to an external clock signal. The memory device includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The first set of data bits are received during a first half of a first clock cycle of the external clock signal. The second set of data bits are received during a second half of the first clock cycle of the external clock signal. In addition, the memory device includes a mask terminal to receive first and second mask bits during a second clock cycle of the external clock signal. The first clock cycle is temporally offset from the second clock cycle. The first mask bit is received during a first half of the second clock cycle, the first mask bit to indicate whether to write the first set of data bits to the array. The second mask bit is received during a second half of the second clock cycle, the second mask bit to indicate whether to write the second set of data bits to the array.

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First Claim