Importance

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Abstract

A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

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First Claim