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Abstract

The invention is directed to techniques which use a test circuit within an FPGA device to obtain a trace of a digital signal used by normal operating circuitry of the FPGA device. The test circuit stores the trace in memory of the FPGA device which is accessible without the need of a logic analyzer (e.g., accessible in a memory mapped or I/O mapped manner). Accordingly, the deficiencies of a conventional built-in approach (e.g., including a mounted connector and connections by sacrificing circuit board area) and soldering approach (e.g., soldering wires to the circuit board requiring time and effort, and increasing the likelihood of signal distortion) for logic analyzer access are avoided. One arrangement of the invention is directed to a computer system having a bus, a processor coupled to the bus, and an FPGA device coupled to the bus. The FPGA device includes (i) normal operating circuitry for performing a normal operating function of the FPGA device, and (ii) a test circuit coupled to the normal operating circuitry. The test circuit is configured to obtain a trace of a digital signal used by the normal operating circuitry. In particular, the test circuit receives, from the processor and through the bus, a control signal enabling capture of the digital signal. The test circuit then captures samples of the digital signal in response to the control signal, and stores the captured samples of the digital signal in the test circuit. The captured samples form the trace of the digital signal. Accordingly, the circuit board designer can avoid the deficiencies of using a logic analyzer, and perform a test-and-debug procedure using the test circuit of the FPGA device.

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First Claim