Timing resynthesis in a multi-clock emulation system
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United States of America Patent
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Jan 20, 2004
Grant Date -
May 1, 2003
app pub date -
Sep 17, 2002
filing date -
Sep 18, 2001
priority date (Note) -
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Abstract
A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.
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