Digital phase/frequency detector, and clock generator and data recovery PLL containing the same
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United States of America Patent
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Jan 27, 2004
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N/A
app pub date -
Dec 23, 1999
filing date -
Dec 23, 1999
priority date (Note) -
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Abstract
An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.
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