Importance

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Abstract

The present invention minimizes power consumption and processing time in a very long instruction word digital signal processor by identifying certain blocks of instructions and placing them in a small, fast buffer for subsequent retrieval and execution. A decoder unit decodes a prefetch instruction flag bit that indicates when instructions are to be prefetched and placed into the buffer. The decoder unit signals a control unit, which sends the instruction code from a memory unit to the buffer and maintains an address mapping table and a program counter. The control unit also sets a select input on a multiplexer to indicate that the multiplexer is to output the prefetch instructions it receives from the buffer. The multiplexer outputs the prefetch instructions to an instruction register that sends the prefetch instructions to appropriate functional units for execution.

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First Claim