Apparatus and method of dynamic and deterministic changes in clock frequency for lower power consumption while maintaining fast interrupt handling
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United States of America Patent
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Jan 27, 2004
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N/A
app pub date -
Dec 5, 2000
filing date -
Jun 22, 2000
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Abstract
An apparatus and method to provide a data processing system with reduced average power consumption while maintaining fast interrupt handling, and/or selectively change clock frequency for accessing memory with various access speeds. In a first embodiment, the invention provides a method to deterministically change a clock frequency between a first clock frequency and a second clock frequency in a data processing system to process operations upon the occurrence of a condition. In a second embodiment, the invention provides a method to change the clock frequency of a data processing system to process operations upon the occurrence of a condition. In a third embodiment, the invention provides a clock divider circuit to produce a core clock signal. In a fourth embodiment, the invention provides a data processing system with a deterministically variable processor clock.
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