Selective formation of top memory electrode by electroless formation of conductive materials

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United States of America Patent

PATENT NO 6686263
SERIAL NO

10314837

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Abstract

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The present invention provides systems and methods that facilitate formation and use of organic memory devices. An electroless plating process is employed that operates at relatively low temperatures and without employing electrical current. The electroless process is utilized to form conductive layers, such as electrodes and the like, from conductive materials. The process includes depositing an activation compound on selected areas and then applying a chemical solution. The chemical solution contains metal ions. Then, a chemical reaction occurs reducing the metal ions and thereby plating the metal ions and forming a conductive layer. Specifically, the electroless process can be employed to form a top electrode of an organic memory device.

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Patent Owner(s)

Patent OwnerAddress
CYPRESS SEMICONDUCTOR CORPORATION198 CHAMPION COURT SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lopatin, Sergey D Santa Clara, CA 82 2467
Ngo, Minh Van Fremont, CA 269 3858

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