Importance

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Abstract

The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on-line CPU provide certain register and memory state information to general purpose registers on an I/O board. The I/O subsystem then provides the register contents to general purpose registers on the off-line CPU board, and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU. At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board. When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line. The I/O subsystem then holds the off-line CPU in the known state by stalling the return of an acknowledgement of the write operation. When the on-line CPU later performs the same write operation, the on-line and the off-line CPUs are then in essentially the same state. The I/O processor may then reset the CPUs to ensure that the off-line CPU goes on line and starts a next operating cycle in lock-step with the reset on-line CPU. The system also dynamically selects a CPU output stream comparison method based on the number of CPUs on line at a given time.

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First Claim