Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
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United States of America Patent
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Feb 10, 2004
Grant Date -
N/A
app pub date -
Sep 22, 1999
filing date -
Sep 22, 1999
priority date (Note) -
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Abstract
A modeling technique for selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a conventional foot print of a ball grid array (BGA) package, or land grid array package (LGA) to improve device reliability. The modeling technique anticipates a routing of traces through the gap resulting from the depopulated solder balls or lands as additional space for routing traces or lines from solder ball or land pads to an exterior surface of a substrate (14) upon which a semiconductor die (20) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls or lands on ever shrinking packages, thereby increasing device reliability.
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