Method for manufacturing semiconductor device employing dielectric layer used to form conductive layer into three dimensional shape
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United States of America Patent
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Feb 10, 2004
Grant Date -
May 2, 2002
app pub date -
Aug 28, 2001
filing date -
Aug 29, 2000
priority date (Note) -
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Abstract
A method for manufacturing a semiconductor device employing a dielectric layer for forming a conductive layer into a three-dimensional shape. The dielectric layer is formed on a substrate in such a manner as to provide an intrinsic etch rate within the layer which increases in the direction of the thickness or depth of the dielectric layer. This variable intrinsic etch rate within the dielectric layer is achieved by changing one of a plurality of deposition variables. Once formed, the dielectric layer is selectively etched to form a through hole to contact a conductive area underlying the dielectric layer. A conductive layer is formed in the through hole, which may be a storage node of a capacitor.
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