Architecture of a PLL with dynamic frequency control on a PLD
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 10, 2004
Grant Date -
N/A
app pub date -
Jun 27, 2001
filing date -
Jun 27, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully