Packaging of integrated circuits and vertical integration
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 17, 2004
Issued Date -
N/A
app pub date -
Nov 16, 2000
filing date -
Dec 6, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully