Graphics processor with pipeline state storage and retrieval
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United States of America Patent
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Feb 17, 2004
Grant Date -
Apr 10, 2003
app pub date -
Nov 7, 2002
filing date -
Aug 20, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
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