Importance

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Abstract

A fuse-controlled, row-redundancy control system and method for a SRAM includes a multi-bit, defective-row storage array of static circuits that are programmed to store one of the address bits of a predetermined defective row of the SRAM and that includes a single fuse. The single fuse is blown to indicate a first state of the one of the address bits and is not blown to indicate a second state of the one address bit. The address bits of the predetermined defective row of the SRAM are compared with corresponding address bits of row-address signals received by the SRAM. The comparator includes a fuseless, exclusive logic circuit and provides a RFLAG control signal that indicates that the stored address bits of the defective row of the SRAM match the respective received row address bits for the SRAM. The RFLAG control signal disables a word line corresponding to the defective row of the SRAM and also enables a redundant SRAM word line corresponding to a redundant SRAM row so that a redundant SRAM row is substituted for the defective row of the SRAM.

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First Claim