Circuit(s), method(s) and architecture for configurable packet re-timing in network repeater hubs
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United States of America Patent
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Feb 24, 2004
Grant Date -
N/A
app pub date -
Sep 23, 1997
filing date -
Sep 23, 1997
priority date (Note) -
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Abstract
A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.
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