Hardware initialization of a synchronous memory
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United States of America Patent
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Feb 24, 2004
Grant Date -
N/A
app pub date -
Jun 30, 2000
filing date -
Jun 30, 2000
priority date (Note) -
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device in one embodiment can comprise non-volatile elements, and control circuitry to read a status of the non-volatile elements during an initialization operation. A reset connection can be provided to receive an externally provided signal and trigger the initialization operation. Further, filter circuitry can be coupled to the reset connection to prevent triggering of the initialization operation if the externally provided signal does not have a duration that exceeds a predetermined minimum duration.
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