Semiconductor device fabrication method for filling high aspect ratio openings in insulators with aluminum
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United States of America Patent
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Mar 2, 2004
Grant Date -
Jul 25, 2002
app pub date -
Jan 4, 2002
filing date -
Jan 5, 2001
priority date (Note) -
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Abstract
A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.
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