Method and apparatus for providing symmetrical output data for a double data rate DRAM
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United States of America Patent
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Mar 9, 2004
Grant Date -
N/A
app pub date -
Aug 31, 2000
filing date -
Aug 31, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
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