Semiconductor leadframe for staggered board attach
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United States of America Patent
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Mar 16, 2004
Grant Date -
Jul 11, 2002
app pub date -
Nov 21, 2001
filing date -
Nov 28, 2000
priority date (Note) -
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Abstract
The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70.+-.1.degree. from the plane and the second segment plurality forms an angle of about 75.+-.1.degree. (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.
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