Register without restriction of number of mounted memory devices and memory module having the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Mar 16, 2004
Grant Date -
Feb 13, 2003
app pub date -
Jul 29, 2002
filing date -
Jul 30, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
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