Spreadsheet driven I/O buffer synthesis process
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United States of America Patent
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Mar 16, 2004
Grant Date -
N/A
app pub date -
Jan 27, 1997
filing date -
Jan 27, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.
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