Configurable logic block with and gate for efficient multiplication in FPGAS
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United States of America Patent
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Mar 16, 2004
Grant Date -
Nov 28, 2002
app pub date -
Jul 9, 2002
filing date -
Jan 21, 1997
priority date (Note) -
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Abstract
An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.
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