Self-aligned split-gate flash cell structure and its contactless flash memory arrays

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United States of America Patent

PATENT NO 6710396
SERIAL NO

10351236

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Abstract

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A self-aligned split-gate flash cell structure of the present invention comprises a ridge-shaped floating-gate layer being formed on a first gate dielectric layer with a first intergate dielectric layer being formed on its top portion and a second intergate dielectric layer being formed on its inner sidewall; a control/select-gate conductive layer being formed at least over a second gate dielectric layer and the first/second intergate dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the control/select-gate conductive layer. The self-aligned split-gate flash cell structure is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

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Patent Owner(s)

Patent OwnerAddress
SILICON-BASED TECHNOLOGY CORP1F NO 23 R&D RD 1 SCIENCE-BASED INDUSTRIAL PARK HSINCHU R O C

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wu, Ching-Yuan Hsinchu, TW 57 975

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