Linearized digital phase-locked loop
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United States of America Patent
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Mar 23, 2004
Grant Date -
N/A
app pub date -
Dec 22, 2000
filing date -
May 12, 2000
priority date (Note) -
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Abstract
A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal, based on the result of step (C), if the result is greater than a predetermined value.
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