Method of analyzing a circuit having at least one structural loop between different channel connected components within the circuit
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United States of America Patent
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Mar 23, 2004
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N/A
app pub date -
Sep 10, 1999
filing date -
Sep 10, 1999
priority date (Note) -
Expired
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Abstract
A method of analyzing a circuit having a structural loop between different channel connected components within the circuit first splits the circuit into its constituent channel connected components (100). The structural loops are then detected and broken (101) before obtaining a pair of boolean functions at each break point (102) by inserting a pair of temporary boolean variables at the break point on a boundary between different channel connected components and analyzing each channel connected component in the structural loop utilizing the pair of temporary boolean variables to obtain the pair of boolean functions representing the functionality of the circuit at the break point. The pair of boolean functions are then analyzed (103) to determine whether the structural loop is sequential in nature, and, if so, the pair of boolean functions is modified (105) in order to remove any dependence in the pair of boolean functions on the pair of boolean variables.
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