Stacked chip package with enhanced thermal conductivity
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United States of America Patent
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Mar 30, 2004
Grant Date -
Mar 4, 2004
app pub date -
Sep 3, 2002
filing date -
Sep 3, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.
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