Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 30, 2004
Grant Date -
N/A
app pub date -
Dec 5, 2002
filing date -
Dec 5, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A stacked multi-chip semiconductor package and a fabrication method thereof are provided. A chip carrier is formed with an opening for receiving a first chip therein, and a second chip is stacked on the first chip and over the opening, wherein the first and second chips are respectively electrically connected to the chip carrier by bonding wires. A first encapsulant is formed to encapsulate first chip and corresponding bonding wires, and a second encapsulant is formed around the second chip to encompass a cavity for receiving the second chip and corresponding bonding wires therein. A lid is attached to the second encapsulant for covering the cavity. This semiconductor package allows high integration and increase in operational performances by virtue of stacked multi-chip structure.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully