Master slave flip-flop circuit functioning as edge trigger flip-flop
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United States of America Patent
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-
Mar 30, 2004
Grant Date -
Feb 12, 2004
app pub date -
Feb 5, 2003
filing date -
Aug 6, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a master latch circuit, input data signal is received in a data through state and is held in a data holding state as output data signal. In a slave latch circuit, the output data signal is received in a data through state and is held and output in a data holding state. In a circuit setting control unit, in response to a clock signal, the disconnection of a first line from a power source and the connection of a second line to a ground terminal in an NMOS transistor are performed to set the master latch circuit and the slave latch circuit to the data through state and the data holding state respectively, and the connection of the first line and the disconnection of the second line are performed to change the states of the latch circuits.
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