Processor having an arithmetic extension of an instruction set architecture
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United States of America Patent
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Mar 30, 2004
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N/A
app pub date -
Jul 30, 1999
filing date -
Jul 30, 1999
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Abstract
A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.
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