Reconfigurable gate array
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United States of America Patent
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Apr 6, 2004
Issued Date -
N/A
app pub date -
Mar 28, 2002
filing date -
Sep 29, 1999
priority date (Note) -
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Abstract
The invention relates to an FPGA (field programmable gate array) with a plurality of functional blocks. An interface enables data and address communication between a processor and the FPGA. The gate array is provided with configurations from a configuration memory. The FPGA also includes a buffer memory for selectively storing configurations from the configuration memory and for the direct selective access, from the FPGA, to any configuration stored in the buffer memory.
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