Latched sense amplifiers as high speed memory in a memory system
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United States of America Patent
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Apr 6, 2004
Issued Date -
N/A
app pub date -
Oct 15, 2002
filing date -
Nov 5, 1991
priority date (Note) -
Expired
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Abstract
A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.
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