Phase manipulation of intertwined bus signals for reduction of hostile coupling in integrated circuit interconnects
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United States of America Patent
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Apr 6, 2004
Grant Date -
N/A
app pub date -
Jan 31, 2001
filing date -
Jan 31, 2001
priority date (Note) -
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Abstract
A bus having improved performance over prior art busses is provided. In one embodiment, the bus includes a first wire having a plurality of intervals, a second wire having a plurality of intervals, and a third wire having a plurality of intervals. The first, second, and third wires are intertwined with each other. Some intervals of the wires include a buffer and some other intervals of the wires include an inverter. In some embodiments, the intervals of the wires that include the buffer are middle wires and in other embodiments, the intervals of the wires the include the buffer are outer wires.
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