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Abstract

A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memory--and which byte--is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into 'words' of varying length. For example, each 'word' may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition. The address translation circuitry performs the division by three operation by multiplying the floating point number by a binary value of approximately one third (0.010101 . . . ). In one embodiment, the two most significant bits of the fractional portion of the result equal the required byte offset (e.g., 0=00 binary; 1=01 binary and 2=10 binary). The binary multiplication process involves shifting and adding of the floating point number. Shifting of the floating point number is equivalent to selecting different portions of the received address for addition. Combinational logic (i.e., logic that is not clocked) may be used to perform the translation process. In this manner, address translation may be completed in as few as a single clock cycle.

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First Claim