Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
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United States of America Patent
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Apr 13, 2004
Grant Date -
Jul 4, 2002
app pub date -
Dec 29, 2000
filing date -
Dec 29, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
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