Importance

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Abstract

A data synchronizer (210) transfers data from a data sending circuit (120) to a data receiving circuit (130). The data sending circuit is synchronous with a first clock (SCLK), and a data receiving circuit is synchronous with a second clock (RCLK). The two clocks have equal frequencies but may be out of phase. The synchronizer includes a circular FIFO. The FIFO entries (FF0-FF3) are written synchronously with the first clock (SCLK). The entries' outputs are connected to a multiplexer (230) whose select signals (RSEL0-RSEL3) are generated synchronously with the second clock (RCLK). Multiple entries make their data items available to the multiplexer at the same time. The sender (120) writes a data item and a data valid flag to the FIFO in each cycle of the first clock. The receiver (130) reads the FIFO in each cycle of the second clock. Synchronization between the first and second clock domains is established at reset to ensure that the second clock domain circuitry does not read any given entry too early or too late. After the reset, no signals are transferred from the second clock domain to the first clock domain. In another embodiment, the first clock is an integer multiple of the second clock or vice versa. The synchronizer can be used to resolve clock skew problems that may be caused by propagation delays of clock signals or by any other factors. Other features are also described.

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First Claim