Apparatus for pipe latch control circuit in synchronous memory device
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United States of America Patent
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-
Apr 20, 2004
Grant Date -
Jun 26, 2003
app pub date -
Oct 1, 2002
filing date -
Dec 24, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device. The apparatus includes a plurality of counting stages for counting in sequence in response to a data output buffer drive signal and a counting signal driver for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.
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