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Abstract

In a configuration for data transmission in a semiconductor memory system, in which data are transmitted between at least one semiconductor memory module and a memory controller controlled by a system clock signal, additional sense clock signal lines are led between the memory controller and the memory modules and, via loops on the memory modules, are led back directly from the memory modules to the memory controller component. By transmitting a sense clock signal from the memory controller to each of the memory modules via the additional sense clock signal lines, the memory controller is able to measure the respective signal propagation time of the sense clock signal and adjust a delay time for the data signals respectively received from the memory modules appropriately. The use of a data strobe signal and the associated disadvantages when testing the memory system or the memory modules is rendered superfluous.

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First Claim