High speed programmable counter architecture
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 20, 2004
Grant Date -
Nov 6, 2003
app pub date -
May 3, 2002
filing date -
May 3, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A high speed programmable counter architecture is disclosed. In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler and an m bit low speed counter. An input signal can be divided by any value equal to or greater than j*2.sup.n. The modulus of division can be provided to the programmable counter in binary form directly, without requiring complex calculations or decoding circuitry. The present invention allows high speed programmable counters to be provided that are capable of dividing by much smaller numbers than conventional counters, including numbers less than 2.sup.n *(2.sup.n -1), wherein n is equal to the number of bits in a high speed prescaler.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully