Selectively processing different size data in multiplier and ALU paths in parallel
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 20, 2004
Grant Date -
N/A
app pub date -
Mar 31, 2000
filing date -
Mar 31, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully