Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
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United States of America Patent
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Apr 20, 2004
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N/A
app pub date -
Dec 11, 2000
filing date -
Dec 11, 2000
priority date (Note) -
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Abstract
A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
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