Low temperature integrated metallization process and apparatus

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6726776
SERIAL NO

09370599

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
APPLIED MATERIALS, INC.SANTA CLARA, CA5532

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fusen Cupestino, CA 67 2342
Guo, Ted Palo Alto, CA 36 812
Mosely, Roderick Craig Pleasanton, CA 27 984
Zhang, Hong Fremont, CA 495 5022

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
4938996 Via filling by selective laser chemical vapor deposition 39 1988
 
SONY CORPORATION (1)
* 5286296 Multi-chamber wafer process equipment having plural, physically communicating transfer means 202 1992
 
TOKYO ELECTRON YAMANASHI LIMITED (25% INTEREST) (1)
5514425 Method of forming a thin film 29 1995
 
FREESCALE SEMICONDUCTOR, INC. (1)
5080933 Selective deposition of polycrystalline silicon 35 1990
 
MICRON TECHNOLOGY, INC. (3)
5032233 Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization 142 1990
5147819 Semiconductor metallization method 83 1991
5240739 Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers 78 1992
 
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM (1)
5292558 Process for metal deposition for microelectronic interconnections 76 1991
 
Inmos Corporation (1)
4784973 Semiconductor contact silicide/nitride process with control for silicide thickness 103 1987
 
YAMAHA CORPORATION (1)
5529955 Wiring forming method 26 1994
 
AT&T LABS, INC. (2)
5102827 Contact metallization of semiconductor integrated-circuit devices 23 1991
5308796 Fabrication of electronic devices by electroless plating of copper onto a metal silicide 60 1993
 
KABUSHIKI KAISHA TOSHIBA (1)
5102826 Method of manufacturing a semiconductor device having a silicide layer 25 1990
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5250465 Method of manufacturing semiconductor devices 32 1992
 
CANON KABUSHIKI KAISHA (1)
5316972 Process for forming deposited film by use of alkyl aluminum hydride and process for preparing semiconductor device 20 1992
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5143867 Method for depositing interconnection metallurgy using low temperature alloy processes 25 1991
 
SHARP KABUSHIKI KAISHA (1)
5312774 Method for manufacturing a semiconductor device comprising titanium 30 1992
 
ADVANCED MICRO DEVICES, INC. (1)
4960732 Contact plug and interconnect employing a barrier lining and a backfilled conductor material 120 1989
 
U.S. PHILIPS CORPORATION (1)
5106781 Method of establishing an interconnection level on a semiconductor device having a high integration density 53 1990
 
CORNELL UNIVERSITY (2)
5023201 Selective deposition of tungsten on TiSi.sub.2 47 1990
5439731 Interconnect structures containing blocked segments to minimize stress migration and electromigration damage 95 1994
 
GLOBALFOUNDRIES INC. (1)
5585673 Refractory metal capped low resistivity metal conductor lines and vias 129 1994
 
SGS-THOMSON MICROELECTRONICS, INC. (1)
5585308 Method for improved pre-metal planarization 69 1995
 
FUJITSU LIMITED (2)
4985750 Semiconductor device using copper metallization 108 1987
5081064 Method of forming electrical contact between interconnection layers located at different layer levels 35 1990
 
MOTOROLA, INC. (2)
4926237 Device metallization, device and method 75 1988
4994410 Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process 116 1990
 
INFINEON TECHNOLOGIES AG (1)
5478780 Method and apparatus for producing conductive layers or structures for VLSI circuits 41 1992
 
ROUND ROCK RESEARCH, LLC (1)
5384284 Method to form a low resistant bond pad interconnect 204 1993
 
APPLIED MATERIALS, INC. (7)
4951601 Multi-chamber integrated process system 827 1989
5028565 Process for CVD deposition of tungsten layer on semiconductor wafer 197 1989
5043299 Process for selective deposition of tungsten on semiconductor wafer 81 1989
5043300 Single anneal step process for forming titanium silicide on semiconductor wafer 98 1990
5250467 Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer 74 1991
5607776 Article formed by in-situ cleaning a Ti target in a Ti+TiN coating process 22 1995
* 5698989 Film sheet resistance measurement 54 1996
 
TEXAS INSTRUMENTS INCORPORATED (3)
4920072 Method of forming metal interconnects 38 1988
4920073 Selective silicidation process using a titanium nitride protective layer 59 1989
5010032 Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects 89 1989
 
MITSUBISHI DENKI KABUSHIKI KAISHA (2)
5429991 Method of forming thin film for semiconductor device 31 1993
5480836 Method of forming an interconnection structure 27 1994
 
TOKYO ELECTRON LIMITED (1)
5380682 Wafer processing cluster tool batch preheating and degassing method 76 1993
 
NORTEL NETWORKS LIMITED (1)
5354712 Method for forming interconnect structures for integrated circuits 312 1992
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
PANASONIC CORPORATION (3)
* 2009/0140,174 Impurity Introducing Apparatus and Impurity Introducing Method 0 2006
7626184 Impurity introducing apparatus and impurity introducing method 1 2008
7622725 Impurity introducing apparatus and impurity introducing method 0 2008
 
INTERMOLECULAR, INC. (2)
* 8409354 Vapor based combinatorial processing 3 2011
* 2012/0090,545 VAPOR BASED COMBINATORIAL PROCESSING 4 2011
 
APPLIED MATERIALS, INC. (2)
7550055 Elastomer bonding of large area sputtering target 21 2005
* 2006/0266,643 Elastomer bonding of large area sputtering target 4 2005
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (2)
* 2008/0166,861 IMPURITY INTRODUCING APPARATUS AND IMPURITY INTRODUCING METHOD 1 2008
* 2008/0210,167 IMPURITY INTRODUCING APPARATUS AND IMPURITY INTRODUCING METHOD 0 2008
* Cited By Examiner