US Patent No: 6,726,776

Number of patents in Portfolio can not be more than 2000

Low temperature integrated metallization process and apparatus

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Abstract

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The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
APPLIED MATERIALS, INC.SANTA CLARA, CA7321

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fusen Saratoga, CA 80 1813
Guo, Ted Palo Alto, CA 47 651
Mosely, Roderick Craig Pleasanton, CA 30 791
Zhang, Hong Shenyang, CN 607 2674

Cited Art Landscape

Patent Info (Count) # Cites Year
 
APPLIED MATERIALS, INC. (7)
4,951,601 Multi-chamber integrated process system 706 1989
5,028,565 Process for CVD deposition of tungsten layer on semiconductor wafer 127 1989
5,043,299 Process for selective deposition of tungsten on semiconductor wafer 80 1989
5,043,300 Single anneal step process for forming titanium silicide on semiconductor wafer 92 1990
5,250,467 Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer 60 1991
5,607,776 Article formed by in-situ cleaning a Ti target in a Ti+TiN coating process 22 1995
5,698,989 Film sheet resistance measurement 54 1996
 
MICRON TECHNOLOGY, INC. (3)
5,032,233 Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization 132 1990
5,147,819 Semiconductor metallization method 78 1991
5,240,739 Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers 78 1992
 
TEXAS INSTRUMENTS INCORPORATED (3)
4,920,072 Method of forming metal interconnects 38 1988
4,920,073 Selective silicidation process using a titanium nitride protective layer 58 1989
5,010,032 Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects 87 1989
 
AT&T Bell Laboratories (2)
5,102,827 Contact metallization of semiconductor integrated-circuit devices 23 1991
5,308,796 Fabrication of electronic devices by electroless plating of copper onto a metal silicide 59 1993
 
CORNELL UNIVERSITY (2)
5,023,201 Selective deposition of tungsten on TiSi.sub.2 47 1990
5,439,731 Interconnect structures containing blocked segments to minimize stress migration and electromigration damage 78 1994
 
FUJITSU LIMITED (2)
4,985,750 Semiconductor device using copper metallization 107 1987
5,081,064 Method of forming electrical contact between interconnection layers located at different layer levels 35 1990
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,143,867 Method for depositing interconnection metallurgy using low temperature alloy processes 25 1991
5,585,673 Refractory metal capped low resistivity metal conductor lines and vias 115 1994
 
KABUSHIKI KAISHA TOSHIBA (2)
5,102,826 Method of manufacturing a semiconductor device having a silicide layer 24 1990
5,514,425 Method of forming a thin film 29 1995
 
MITSUBISHI DENKI KABUSHIKI KAISHA (2)
5,429,991 Method of forming thin film for semiconductor device 31 1993
5,480,836 Method of forming an interconnection structure 27 1994
 
MOTOROLA, INC. (2)
4,926,237 Device metallization, device and method 74 1988
4,994,410 Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process 116 1990
 
ADVANCED MICRO DEVICES, INC. (1)
4,960,732 Contact plug and interconnect employing a barrier lining and a backfilled conductor material 119 1989
 
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM (1)
5,292,558 Process for metal deposition for microelectronic interconnections 71 1991
 
CANON KABUSHIKI KAISHA (1)
5,316,972 Process for forming deposited film by use of alkyl aluminum hydride and process for preparing semiconductor device 20 1992
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,080,933 Selective deposition of polycrystalline silicon 33 1990
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5,250,465 Method of manufacturing semiconductor devices 32 1992
 
INFINEON TECHNOLOGIES AG (1)
5,478,780 Method and apparatus for producing conductive layers or structures for VLSI circuits 35 1992
 
Inmos Corporation (1)
4,784,973 Semiconductor contact silicide/nitride process with control for silicide thickness 103 1987
 
NORTEL NETWORKS LIMITED (1)
5,354,712 Method for forming interconnect structures for integrated circuits 294 1992
 
ROUND ROCK RESEARCH, LLC (1)
5,384,284 Method to form a low resistant bond pad interconnect 112 1993
 
SGS-THOMSON MICROELECTRONICS, INC. (1)
5,585,308 Method for improved pre-metal planarization 62 1995
 
SHARP KABUSHIKI KAISHA (1)
5,312,774 Method for manufacturing a semiconductor device comprising titanium 30 1992
 
SONY CORPORATION (1)
5,286,296 Multi-chamber wafer process equipment having plural, physically communicating transfer means 190 1992
 
TOKYO ELECTRON LIMITED (1)
5,380,682 Wafer processing cluster tool batch preheating and degassing method 71 1993
 
U.S. PHILIPS CORPORATION (1)
5,106,781 Method of establishing an interconnection level on a semiconductor device having a high integration density 53 1990
 
YAMAHA CORPORATION (1)
5,529,955 Wiring forming method 25 1994
 
ZIV, ALAN R. (57.5 PERCENT) (1)
4,938,996 Via filling by selective laser chemical vapor deposition 39 1988

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
PANASONIC CORPORATION (2)
7,626,184 Impurity introducing apparatus and impurity introducing method 1 2008
7,622,725 Impurity introducing apparatus and impurity introducing method 0 2008
 
APPLIED MATERIALS, INC. (1)
7,550,055 Elastomer bonding of large area sputtering target 11 2005
 
INTERMOLECULAR, INC. (1)
8,409,354 Vapor based combinatorial processing 1 2011

Maintenance Fees

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11.5 Year Payment $7400.00 $3700.00 $1850.00 Oct 27, 2015
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Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
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