Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array
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United States of America Patent
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Apr 27, 2004
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app pub date -
Nov 12, 2002
filing date -
Nov 12, 2002
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Abstract
The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA having logic clusters, wherein each logic cluster further comprises a buffer. The method of the present system comprises a method of determining which buffers situated in each logic cluster are located in the best position in the post-placement user netlist to decrease the capacitance in the user netlist.
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