Method and apparatus for reducing PLL lock time
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United States of America Patent
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-
May 4, 2004
Grant Date -
N/A
app pub date -
May 9, 2000
filing date -
May 9, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The lock time is reduced in a phase locked loop frequency synthesizer that has both active modes and standby modes. In the active mode the frequency synthesizer operates to maintain a stable frequency output. The standby or sleep mode is used to reduce power consumption when the frequency synthesizer is not required to provide a frequency output. When the synthesizer is placed in standby mode the most recent value of the Voltage Controlled Oscillator (VCO) tuning voltage is maintained on the VCO tuning control line of the frequency synthesizer. The voltage is maintained on the VCO tuning output pin in Integrated Circuit (IC) frequency synthesizers. The voltage error on the VCO tuning pin is minimized thereby minimizing the lock time of the frequency synthesizer.
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