Importance

Loading Importance Indicators...

Abstract

A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal 'stripes' therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction. Sense amplifier circuitry for detecting the state of selected memory cells is disposed along stripes extending in a second direction, substantially perpendicular to the first direction. Column decode circuitry is disposed along one edge of each memory sub-array such that column select signals propagate along a direction substantially parallel to the stripes of row decoder circuitry. Array control circuitry for generating various control signals activated throughout the course of a memory access (read and/or write) cycle is disposed proximal the column decode circuitry, such that the various control signals propagate along a direction substantially parallel to the column select signals. Elongate power straps for providing operational power to the sub-arrays extend over the sub-arrays in a direction substantially parallel to the column select signals and the control signals.

Loading the Abstract Image...

First Claim